This invention relates to a pattern transfer process for making integrated-circuit devices and, more particularly, to an improved method for transferring a pattern defined in resist into the planarizing layer of a multilevel resist structure.
Increasing miniaturization of semiconductor integrated-circuit devices is the basis for reduced unit cost per function and for improved performance. Feature sizes in very-large-scale-integrated (VLSI) devices thus continue to get smaller. Some predict that minimum feature sizes in VLSI devices in actual production will certainly be less than one micrometer (.mu.m) before 1990.
As feature sizes of VLSI devices decrease, processing requirements for fabricating the devices become more critical. These requirements include the availability of resists characterized by extremely high sensitivity and resolution. Moreover, for improved resolution and linewidth control, such resists must in many cases of practical importance be included in multilevel resist structures such as the so-called trilevel structure described in U.S. Pat. No. 4,244,799 and in "High Resolution, Steep Profile, Resist Patterns" by J. M. Moran and D. Maydan, The Bell System Technical Journal, Vol. 58, No. 5, May-June 1979, pages 1027-1036. Such a trilevel structure typically includes a top resist layer, an intermediate masking layer and a bottom planarizing layer.
In a trilevel structure as heretofore proposed, a lithographically defined pattern in the resist layer is first transferred into the intermediate masking layer. Subsequently, utilizing the pattern in the intermediate layer as a mask, the planarizing layer is patterned. This last-mentioned transfer step is, for example, carried out in a reaction chamber by dry etching techniques utilizing an oxygen plasma to pattern the planarizing layer, as described in the aforedescribed references.
As feature sizes in integrated-circuit devices decrease to one .mu.m and below, it has become exceedingly difficult in practice to maintain high quality linewidth control at relatively high etching rates when utilizing an oxygen plasma to pattern the planarizing layer of a multilevel resist structure. By adjusting the rate of flow of oxygen into the reaction chamber and the value of the bias voltage on the electrode that holds the device to be etched, the characteristics of the etching process can be selectively varied. But adequate linewidth control is usually achieved in this manner at the expense of etching rate. And attempts to increase etching rate typically degrade linewidth control and also may cause radiation damage to the device being etched.
Accordingly, efforts have been directed by workers skilled in the art at trying to devise improved etching techniques for transferring a pattern into the planarizing layer of a multilevel resist structure. In particular, these efforts have been directed at trying to achieve good linewidth control, high etching rates and negligible radiation damage to the device being etched. It was recognized that these efforts, if successful, had the potential to significantly increase the quality and decrease the cost of extremely fine-feature integrated-circuit devices.